1. Field of the Invention
The present invention relates to a thin film transistor substrate (hereinafter also referred to as “TFT substrate”) having thin film transistors (hereinafter also referred to as “TFTs”) integrated thereon and a display having the same and, more particularly, to a TFT substrate on which TFTs utilizing semiconductor films made of polycrystalline silicon (polysilicon) or the like silicon are integrated and a display having the same.
2. Description of the Related Art
TFT substrates are used as substrates for driving active matrix liquid crystal display panels and EL (electroluminescence) display panels. Recently, polysilicon having high electron mobility is used for semiconductor layers to integrate not only TFTs for pixels but also a gate driver circuit and a data driver circuit that are peripheral circuits on the same substrate.
In such cases, driver circuits utilizing TFTs are normally constituted by complementary MOS (CMOS) transistors that are combinations of n-type and p-type transistors. The n-type TFTs are frequently formed with LDDs (lightly doped drains) that are low density impurity regions in order to suppress the degradation of characteristics due to the hot carrier phenomenon (hereinafter referred to as “hot carrier degradation”) and the occurrence of an off leak current.
A description will now be made with reference to FIGS. 12A to 13C on a method of manufacturing TFTs of a TFT substrate to be used for a liquid crystal display panel (a first example of the related art) in which a driver circuit is constituted by CMOS transistors and in which an n-type TFT is provided with an LDD structure. In FIGS. 12A to 13C, an n-type TFT and a p-type TFT are shown on the left and right sides of the figures, respectively.
As shown in FIG. 12A, a SiO2 film is first formed on a transparent insulated substrate 101 made of glass to a thickness of about 80 nm to provide a buffer layer 102. An amorphous silicon film is thereafter formed using plasma CVD, and the amorphous silicon is then crystallized by annealing it with an excimer laser to form a polysilicon semiconductor layer 103 having a thickness of about 50 nm. Next, the semiconductor layer 103 is patterned to form island-like semiconductor layers 103a and 103b. Then, a SiO2 film is formed on the semiconductor layers 103a and 103b to a thickness of about 100 nm to provide a gate insulation film 104. Subsequently, a Cr film having a thickness of about 400 nm is formed and then patterned to provide gate electrodes 105a and 105b. 
As shown in FIG. 12B, a resist is then applied and patterned to form a resist mask R106 such that it covers a region to become LDDs of the n-type TFT and the gate electrodes. Next, etching is performed using the resist mask R106 as an etching mask to form gate insulation films 104a and 104b. The gate insulation film 104a and the gate electrode 105a of the n-type TFT are formed like steps. Thereafter, the resist mask R106 is removed.
As shown in FIG. 12C, a resist is then applied and patterned to form a resist mask R107 such that it covers the p-type TFT as a whole. Next, an impurity such as phosphorus is implanted at low acceleration and in a high dose amount (that are 10 keV and 1×1015 cm−2, respectively, for example) using the resist mask R107, the gate electrode 105a and the gate insulation film 104a as masks to form source and drain regions 1031 of the n-type TFT in the semiconductor layer. Subsequently, an impurity such as phosphorus is implanted through the gate insulation film 104a at high acceleration and in a low dose amount (that are 90 KeV and 5×1013 cm−2, respectively, for example) using the resist mask R107 and the gate electrode 105a as masks to form LDD regions 1032. Referring to the first implantation of an impurity such as phosphorus, while the impurity must be implanted in the source and drain regions in a great amount, it is implanted at low acceleration and in a high dose amount because the gate insulation film 104a has been removed to leave no obstacle. Referring to the second implantation of an impurity such as phosphorus, while there is no need for implanting the impurity in a great amount because the purpose is to form LDDs, the implantation is performed at high acceleration and in a low dose amount because the impurity must be implanted through the gate insulation film 104a. The impurity such as phosphorus is not implanted in a channel region 1033 because the gate electrode 105a is used as a mask in both of the two rounds of implantation of the impurity such as phosphorus. There resist mask R107 is thereafter removed.
Next, as shown in FIG. 13A, a resist is applied and patterned to form a resist mask R108 such that it covers the n-type TFT as a whole. Next, an impurity such as boron is implanted with a predetermined acceleration energy and in a predetermined dose amount (that are 10 keV and 1×1015 cm−2, respectively, for example) using the resist mask R108 and the gate electrode 105b as masks to form source and drain regions 1035 of the p-type TFT in the semiconductor layer. Since the gate electrode 105b serves as a mask, the impurity such as boron is not implanted in a channel region 1036. The resist mask R108 is thereafter removed.
Next, as shown in FIG. 13B, the implanted impurities such as phosphorus and boron are activated by irradiating them with an excimer laser. While the source and drain regions 1031 of the n-type TFT and the source and drain regions 1035 of the p-type TFT are irradiated with laser light because there is no obstacle at all, it should be noted that the LDD regions 1032 are irradiated with laser light through the gate insulation film 104a. 
Next, as shown in FIG. 13C, a SiN film is formed to a thickness of about 300 nm to provide a layer insulation film 109, and contact holes are provided in the layer insulation film 109. A Mo film is formed to a thickness of about 300 nm and patterned to provide wirings 110. Thus, then-type TFT and p-type TFT are completed. Although not shown, a protective film and pixel electrodes are formed to complete the TFT substrate.
In most cases, as shown in FIGS. 12A to 13C, the gate electrode 105a and the gate insulation film 104a of the n-type TFT are processed in the form of steps; implantation is performed at low acceleration and in a high dose amount using the gate electrode 105a and the gate insulation film 104a as masks to form the source and drain regions; and implantation is performed through the gate insulation film 104a at high acceleration and in a low dose amount using the gate electrode 105a as a mask to form the LDD regions. While FIGS. 12A to 13C show a structure in which the p-type TFT has no LDD region, the gate electrode 105b and the gate insulation film 104b of the p-type TFT may also be processed in the form of steps to form LDD regions.
A description will now be made with reference to FIGS. 14A to 15C on a method of manufacturing a TFT substrate to be used for a liquid crystal display panel (a second example of the related art) in which a single substrate is formed with TFTs for a low voltage capable of a high speed operation that constitute a part of a driver circuit, pixel TFTs for a high voltage for driving a liquid crystal, and a part of a driver circuit. FIGS. 14A to FIG. 15C illustrate a method of manufacturing an n-type TFT. In FIGS. 14A to 15C, a TFT for a low voltage and a TFT for a high voltage are shown on the left and right sides of the figures, respectively.
As shown in FIG. 14A, a SiO2 film is first formed on a transparent insulated substrate 201 made of glass to a thickness of about 80 nm to provide a buffer layer 202. An amorphous silicon film is thereafter formed using plasma CVD, and the amorphous silicon is then crystallized by annealing it with an excimer laser to form a polysilicon semiconductor layer 203 having a thickness of about 50 nm. Next, the semiconductor layer 203 is patterned to form island-like semiconductor layers 203a and 203b. 
As shown in FIG. 14B, a SiO2 film is then formed on the semiconductor layers 203a and 203b to a thickness of about 30 nm to provide a gate insulation film 204 for the TFT for a low voltage. Subsequently, a Cr film is formed to a thickness of about 400 nm and patterned to provide a gate electrode 205a and a gate insulation film 204a of the TFT for a low voltage. Thus, the gate insulation film 204a and the gate electrode 205a are formed only on the TFT for a low voltage.
Next, as shown in FIG. 14C, a SiO2 film is formed throughout the substrate to a thickness of about 100 nm to provide a gate insulation film 206 of the TFT for a high voltage. Next, a Cr film is formed to a thickness of about 400 nm and patterned to provide a gate electrode 207b of the TFT for a high voltage. Thus, the TFT for a high voltage is formed with the gate electrode 207b. The thickness of the gate insulation film 204a of the TFT for a low voltage is relatively small, and the thickness of the gate insulation film 206 of the TFT for a high voltage is relatively great.
Next, a resist is then applied and patterned to form a resist mask. The gate insulation film 206 is then etched using the resist mask as an etching mask as shown in FIG. 15A. The gate insulation film 206 is etched such that it becomes wider than the gate electrode 207b of the TFT for a high voltage and such that it is left only in the region of the TFT for a high voltage. The resist mask is thereafter removed. At this stage, the gate electrode 207b and the gate insulation film 206b are formed like steps at the TFT for a high voltage.
Next, an impurity such as phosphorous is implanted at low acceleration and in a high dose amount (that are 10 keV and 1×1015 cm−2, respectively, for example) using the gate electrode 205a, the gate electrode 207b and the gate insulation film 206b as masks to form source and drain regions 2031 of the TFT for a low voltage and source and drain regions 2035 of the TFT for a high voltage. Subsequently, an impurity such as phosphorous is implanted through the gate insulation film 206b into the semiconductor layer 203b at high acceleration and in a low dose amount (that are 90 keV and 5×1013 cm−2, respectively, for example) using the gate electrode 205a and the gate electrode 207b as masks to form LDD regions 2036 of the TFT for a high voltage.
While the source and drain regions must be doped with a great amount of impurity at the first implantation of an impurity such as phosphorous, implantation is performed at low acceleration and in a high dose amount because the gate insulation film 206 has been removed to leave no obstacle. On the contrary, while there is no need to implant a great amount of impurity at the second implantation of an impurity such as phosphorous because LDDs are to be formed, implantation is performed at high acceleration and in a low dose amount because the implantation must be performed through the gate insulation film 206b. Since the gate electrodes 205a and 207b are used as masks at both of the two rounds of implantation of the impurity such as phosphorous, the impurity such as phosphorous is not implanted in the channel regions 2032 and 2037.
Although not shown in FIGS. 14A to 15C, since the peripheral circuits such as the drivers are normally constituted by CMOS transistors, it is necessary to implant an impurity such as phosphorous into TFTs (including pixel TFTs) to become n-type TFTs after covering TFT to become p-type TFTs with a resist mask and to implant an impurity such as boron in the TFTs to become p-type TFTs after covering the TFT to become n-type TFTs with a resist mask.
Next, as shown in FIG. 15B, the implanted impurities such as phosphorous and boron are activated by irradiating them with an excimer laser. While the source and drain regions 2031 of the TFT for a low voltage and the source and drain regions 2035 of the TFT for a high voltage are directly irradiated with laser light because there is no obstacle at all, it should be noted that the LDD regions 2036 are irradiated with laser light through the gate insulation film 206b. 
Next, as shown in FIG. 15C, a SiN film is formed to a thickness of about 300 nm to provide a layer insulation film 208, and contact holes are provided in the layer insulation film 208. A Mo film is formed to a thickness of about 300 nm and patterned to provide wirings 209. Thus, the TFT for a low voltage and the TFT for a high voltage are completed. Although not shown, a protective film and pixel electrodes are formed further to complete the TFT substrate.
As thus described, in the TFT for a high voltage, the gate insulation film 206b wider than the gate electrode 207b is provided on the semiconductor layer 203b to form a stepped structure similar to that in the first example of the related art. The LDD regions 2036 are thus formed. In the TFT for a low voltage, since the gate electrode 205a and the gate insulation film 204a have the same width, no LDD region is formed.
JP-A-2001-168346 has disclosed a technique in which an impurity is implanted twice to provide an LDD structure and in which the dimensions of a gate electrode to be used as a mask are changed between the first and second rounds of implantation depending on the length of the LDD. Metal oxidation or dry etching is used to change the dimensions of the gate electrode used as a mask, and an elaborate photoresist is provided to allow the gate electrode to be dry-etched with high accuracy. However, the use of such a technique results in a problem in that it is not easy to control the length of the LDD because no mask is used to change the dimensions of the gate electrode.
JP-A-2000-36598 has disclosed a technique in which TFTs having different LDD structures are simultaneously fabricated on the same substrate. According to the publication, a highly heat resistant Ta film or a Ta-based film is used as a wiring material which is further covered by a protective layer. This allows a heating process at a high temperature, and the protective film is used as an etching stopper to provide TFTs having LDD structures formed by a self-aligning process utilizing sidewalls in the section of peripheral circuits and to provide TFTs having LDD structures formed by a non-self-aligning process utilizing an insulator in the section of a pixel matrix. In addition to the above-cited technical disclosure, the publication points out a need for etching a gate insulation film because of a need for forming the gate insulation film on the entire surface with a small thickness that is adapted to the peripheral driving circuit section prior to the formation of gate electrodes and for forming the gate insulation film again such that it has a greater thickness in the pixel matrix section. Since the gate insulation film is subjected to anisotropic etching after forming an insulation film on the gate electrodes and covering regions of the pixel matrix section with a resist to become LDDs, LDDs having a great LDD length are formed in the pixel matrix section using mask registration, and LDDs that are self-aligned using sidewalls are formed in the circuit section. However, it is not possible to form TFTs having no LDD selectively.
Further, JP-A-9-191111 has disclosed a method of fabricating a semiconductor device, characterized in that it has a step of integrally fabricating an n-channel type thin film transistor and a p-channel type thin film transistor on the same substrate, a porous anodic oxide film being selectively formed on a side of a gate electrode made of a material that can be anodized at the same step, a step of adding an impurity that imparts n-type properties using the anodic oxide film as a mask, a step of removing the anodic oxide film, a step of adding an impurity that imparts n-type properties using the gate electrode as a mask to form an LDD region under the region where the anodic oxide film has existed and a step of adding an impurity that imparts p-type properties while masking the region to become the n-channel type thin film transistor selectively. According to the technique in the publication, it is necessary to anodize the gate electrode. Further, all TFTs are formed with LDDs having the same length, and it is not possible to form n-type TFTs having no LDD selectively.
As described above with reference to the first example of the related art, according to methods of manufacturing a TFT substrate in which LDD are formed by forming a semiconductor layer and a gate insulation film in the form of steps, an entire surface of a TFT substrate is frequently irradiated with an excimer laser to activate an impurity that has been introduced therein at a low temperature. While the gate insulation film 104a is formed on the LDD regions 1032, no gate insulation film is formed on the source and drain regions 1031 and 1035. Therefore, energy that is actually absorbed by the LDD regions 1032 is different from that absorbed by the source and drain regions 1031 and 1035 because of the effect of optical interference, which results in a problem in that it is not easy to optimize energy for activation. Further, the improvement of TFT performance has resulted in a trend toward thinner gate insulation films. When the gate insulation film 104a becomes thinner, it becomes less capable of masking impurity ions when the source and drain regions 1031 and 1035 are doped with the impurity. Thus, a part of impurity ions are implanted in the LDD regions 1032 too, which results in a problem in that it becomes difficult to control the density of the impurity in the LDD regions 1032 to achieve a low density.
The method of manufacturing a TFT substrate as described with reference to the second example of the related art has the following problems in addition to the problems with the first example of the related art. The gate insulation film 204 for the TFT for a low voltage is once formed on the semiconductor layer 203b for the TFT for a high voltage, and the gate insulation film 204 is thereafter removed through etching. Since the etching is normally dry etching, the semiconductor layer 203b of the TFT for a high voltage is very much vulnerable to plasma damage attributable to the etching. This results in a problem in that the characteristics and reliability of the TFT for a high voltage are degraded. Referring to the TFT for a low voltage, since the gate electrode 205a and the gate insulation film 204a have the same width, a leak current is likely to flow between the gate electrode 205a and the semiconductor layer 203a (the source and drain regions 2031 and the channel region 2032) because of a small amount of impurity or contaminated ions that are left on a sidewall of the gate insulation film 204a at manufacturing processes. In addition, this tendency is more significant for the TFT for a low voltage because the gate insulation film 204a of the same has a smaller thickness. This results in a problem in that the reliability of the TFT for a low voltage is also reduced.
Further, in order to load circuits having higher functions on a TFT substrate integral with peripheral circuits in the future, elements may be made finer by reducing their channel lengths to increase the operating speeds of a logic circuit section and a signal processing circuit section, and LDDs may be eliminated even from n-type TFTs. For this purpose, a lower operating voltage must be achieved by making the thickness of gate insulation films of TFTs of the logic circuit section and the signal processing circuit section smaller compared to that in pixel TFTs which require a somewhat high voltage (in the range from 10 V to 30 V, for example) to achieve liquid crystal or EL driving or that in a part of a driver circuit that directly drives the pixel TFTs. The reason is that a reduction of the thickness of a gate insulation film allows a threshold voltage and hence an operating voltage to be decreased and that degradation attributable to hot carriers can therefore be suppressed without increasing a channel length or forming LDDs.